Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMINP (vector, 8B)

Test 1: uops

Code:

  uminp v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000

Test 2: Latency 1->2

Code:

  uminp v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->3

Code:

  uminp v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420020012110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  uminp v0.8b, v8.8b, v9.8b
  uminp v1.8b, v8.8b, v9.8b
  uminp v2.8b, v8.8b, v9.8b
  uminp v3.8b, v8.8b, v9.8b
  uminp v4.8b, v8.8b, v9.8b
  uminp v5.8b, v8.8b, v9.8b
  uminp v6.8b, v8.8b, v9.8b
  uminp v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400488010910180008100800123003200448011020080014200160028180000100
80204400448010710180006100800103003200368010820080012200160024180000100
80204400348010510180004100800083003201928015020080060200160026180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100
80204400348010510180004100800083003200368010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244018180027218000620800100650320052800322008001720160000118000010
800244003480021218000020800000650320000800202008000020160000118000010
800244003480021218000020800000640320208800742008006020160034118000010
800244004180021218000020800000650320000800202008000020160000118000010
800244003480021218000020800000650320000800202008000020160000118000010
800244003480021218000020800000650320000800202008000020160000118000010
80024400348002121800002080000471119587910201224404170869825957636057020160000118000010
800244003580021218000020800000650320000800202008000020160000118000010
800244003480021218000020800000650320000800202008000020160096118000010
800244003480021218000020800000650320000800202008000020160000118000010