Icestorm: UMLSL (by element, 2D) measurements

Code:

  umlsl v0.2d, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  umlsl v0.2d, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10044	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  umlsl v0.2d, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	2160	39841	21427	769548	14921	3897	2582	10069	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30085	10029	21	10008	20	10033	70	769451	10053	20	10038	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	69	769451	10053	20	10041	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  umlsl v0.2d, v1.2s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30132	1	10000	100
10204	30135	10117	101	10016	100	10066	303	770443	10200	202	10123	200	30375	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30083	10109	101	10008	100	10033	307	769451	10135	202	10046	204	30252	3	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  umlsl v0.2d, v8.2s, v9.s[1]
  movi v1.16b, 0
  umlsl v1.2d, v8.2s, v9.s[1]
  movi v2.16b, 0
  umlsl v2.2d, v8.2s, v9.s[1]
  movi v3.16b, 0
  umlsl v3.2d, v8.2s, v9.s[1]
  movi v4.16b, 0
  umlsl v4.2d, v8.2s, v9.s[1]
  movi v5.16b, 0
  umlsl v5.2d, v8.2s, v9.s[1]
  movi v6.16b, 0
  umlsl v6.2d, v8.2s, v9.s[1]
  movi v7.16b, 0
  umlsl v7.2d, v8.2s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40502	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40099	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240144	1	160000	100
160204	40098	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40096	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240039	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43845	80019	11	80008	10	80012	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41326	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40440	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40407	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40402	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  umlsl v0.2d, v12.2s, v13.s[1]
  umlsl v1.2d, v12.2s, v13.s[1]
  umlsl v2.2d, v12.2s, v13.s[1]
  umlsl v3.2d, v12.2s, v13.s[1]
  umlsl v4.2d, v12.2s, v13.s[1]
  umlsl v5.2d, v12.2s, v13.s[1]
  umlsl v6.2d, v12.2s, v13.s[1]
  umlsl v7.2d, v12.2s, v13.s[1]
  umlsl v8.2d, v12.2s, v13.s[1]
  umlsl v9.2d, v12.2s, v13.s[1]
  umlsl v10.2d, v12.2s, v13.s[1]
  umlsl v11.2d, v12.2s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60111	120105	101	120004	100	120008	300	480044	120110	200	120014	200	360039	1	120000	100
120205	60070	120143	101	120042	100	120054	300	480044	120110	200	120014	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60255	120255	101	120154	100	120158	300	480044	120110	200	120014	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60193	120017	11	120006	10	120010	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60039	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	0	30	0	480000	120010	20	0	120000	20	360000	1	120000	10

UMLSL (by element, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations