Icestorm: UMOV (S to W) measurements

Code:

  umov w0, v0.s[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Code:

  umov w0, v0.s[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10003	10003	200	10003	10003	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10021	300	1245534	899505	20136	200	10026	10026	200	10002	10002	10001	10000	10100
20204	70036	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	70033	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10003	10003	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10026	10026	10003	10000	10010
20024	70043	30011	10011	10000	10000	10	10000	10000	30	1250524	900564	20010	20	10000	10000	20	10086	10085	10013	10000	10010
20024	70051	30011	10011	10000	10000	10	10000	10000	30	1248904	899394	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70038	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248958	899433	20010	20	10000	10000	20	10128	10127	10019	10000	10010

Test 3: throughput

Count: 8

Code:

  umov w0, v8.s[1]
  umov w1, v8.s[1]
  umov w2, v8.s[1]
  umov w3, v8.s[1]
  umov w4, v8.s[1]
  umov w5, v8.s[1]
  umov w6, v8.s[1]
  umov w7, v8.s[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80064	80029	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80036	80015	80100
80204	80040	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80205	80068	160133	80115	80018	100	80024	300	320088	80123	200	80036	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320083	80122	200	80035	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80039	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80024	80049	160021	80021	80000	20	80002	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80036	80025	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010

UMOV (S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations