Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQADD (scalar, D)

Test 1: uops

Code:

  uqadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->2

Code:

  uqadd d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430085101111031000810210033300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020010110000100
1020430033101011011000010010000307769997101682021008320020008110000100
1020430033101011011000010010000307769997101682021008420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430084101111031000810210033300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020168110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020088110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062020000111000010
10024300331002121100002010000707689051002020100002020076111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10025300661002721100062010031707689051002020100002020000111000010

Test 3: Latency 1->3

Code:

  uqadd d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020088110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100042020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10025300661002721100062010031070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10025300661002721100062010031070076890510020200100002020000111000010
10024300331002121100002010000444472397695891018914044100842020012111000010

Test 4: throughput

Count: 8

Code:

  uqadd d0, d8, d9
  uqadd d1, d8, d9
  uqadd d2, d8, d9
  uqadd d3, d8, d9
  uqadd d4, d8, d9
  uqadd d5, d8, d9
  uqadd d6, d8, d9
  uqadd d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
802044008280107101800060100800103003200448011020080014200160026180000100
802044003580107101800060100800103003200368010820080012200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100
802044003580105101800040100800083003200448011020080013200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100
802054007080145101800440100800563003200448011020080013200160024180000100
802044003580105101800040100800083003200368010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800254019680065218004420800566532005280032208001820160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244033480219218019820801986532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160096118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010