Icestorm: UQSHL (immediate, vector, 2D) measurements

Code:

  uqshl v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  uqshl v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10006	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10006	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	0	300	0	509248	10100	200	0	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  uqshl v0.2d, v8.2d, #3
  uqshl v1.2d, v8.2d, #3
  uqshl v2.2d, v8.2d, #3
  uqshl v3.2d, v8.2d, #3
  uqshl v4.2d, v8.2d, #3
  uqshl v5.2d, v8.2d, #3
  uqshl v6.2d, v8.2d, #3
  uqshl v7.2d, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40054	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80014	1	0	80000	100
80205	40070	80140	101	80039	0	100	80051	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
37338	29940	37179	1091	35505	583	1041	35525	300	320036	80108	200	80012	200	0	80014	1	0	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	202	0	80062	2	0	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320192	80150	200	80060	27409	17802	80147	12483	7641	80043	13781
80204	40053	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80014	1	0	80000	100
80204	40034	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40100	80027	21	80006	20	80010	70	320044	80030	20	80016	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80025	40069	80063	21	80042	20	80054	70	320000	80020	20	80000	20	80000	11	80000	10

UQSHL (immediate, vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations