Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQSHRN (H)

Test 1: uops

Code:

  uqshrn b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  uqshrn b0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620010004110000100
1020430033101011011000010010000030007692471013120001004620010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000697683561005320100452010000111000010
10024300331002121100002010000707689051002020100002010038111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010048111000010
10024300331002121100002010000697692471005120100482010004111000010
10024300841002921100082010033707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  uqshrn b0, h8, #3
  uqshrn b1, h8, #3
  uqshrn b2, h8, #3
  uqshrn b3, h8, #3
  uqshrn b4, h8, #3
  uqshrn b5, h8, #3
  uqshrn b6, h8, #3
  uqshrn b7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440080801071018000610080010300320036801082008001220080012180000100
8020440035801071018000610080010300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080064180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244013380029218000802080012703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003980021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010
800244003580021218000002080000703200008002020800002080000118000010