Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQXTN2 (4S)

Test 1: uops

Code:

  uqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  uqxtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000300768905101002001000620020008110000100
10204300331010110110000010010000300769232101312001004520020012110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020012110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020008110000100
10204300331010110110000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002020096111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10025300661002721100062010031707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  uqxtn2 v0.8h, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300769247101312001004420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076924710051200100442020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000066076924710051200100482020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uqxtn2 v0.8h, v8.4s
  movi v1.16b, 0
  uqxtn2 v1.8h, v8.4s
  movi v2.16b, 0
  uqxtn2 v2.8h, v8.4s
  movi v3.16b, 0
  uqxtn2 v3.8h, v8.4s
  movi v4.16b, 0
  uqxtn2 v4.8h, v8.4s
  movi v5.16b, 0
  uqxtn2 v5.8h, v8.4s
  movi v6.16b, 0
  uqxtn2 v6.8h, v8.4s
  movi v7.16b, 0
  uqxtn2 v7.8h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048280110101800091008001330032005280112200800122001600241160000100
1602044012180109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5055

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244387380020118000910800133032000080010208000020160000116000010
1600244122780011118000010800003032000080010208000020160000116000010
1600244047780011118000010800003032000080010208000020160000116000010
1600244043980011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244039080011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244043380011118000010800003032005680023208001320160000116000010

Test 5: throughput

Count: 16

Code:

  uqxtn2 v0.8h, v16.4s
  uqxtn2 v1.8h, v16.4s
  uqxtn2 v2.8h, v16.4s
  uqxtn2 v3.8h, v16.4s
  uqxtn2 v4.8h, v16.4s
  uqxtn2 v5.8h, v16.4s
  uqxtn2 v6.8h, v16.4s
  uqxtn2 v7.8h, v16.4s
  uqxtn2 v8.8h, v16.4s
  uqxtn2 v9.8h, v16.4s
  uqxtn2 v10.8h, v16.4s
  uqxtn2 v11.8h, v16.4s
  uqxtn2 v12.8h, v16.4s
  uqxtn2 v13.8h, v16.4s
  uqxtn2 v14.8h, v16.4s
  uqxtn2 v15.8h, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800881601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103006400361601082001600122003200281160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200281160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204801101601531011600521001600563006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160205800701601411011600401001600523006400441601102001600142003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248015716001511160004010160008306400361600182016001220320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320124116000010
1600248004116001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320130116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320024116000010
1600248003916001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010