Icestorm: URECPE (vector, 2S) measurements

Code:

  urecpe v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  urecpe v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10006	20	10006	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	69	379850	10038	20	10033	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  urecpe v0.2s, v8.2s
  urecpe v1.2s, v8.2s
  urecpe v2.2s, v8.2s
  urecpe v3.2s, v8.2s
  urecpe v4.2s, v8.2s
  urecpe v5.2s, v8.2s
  urecpe v6.2s, v8.2s
  urecpe v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80205	80070	80119	101	80018	0	100	80023	300	320005	80101	200	80008	200	80068	1	80000	100
85001	92649	84240	2581	80069	1590	2421	80066	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100
80204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	80008	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	80050	80021	21	80000	20	80002	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320092	80044	20	80036	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320092	80044	20	80036	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	80035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80040	11	0	80000	10

URECPE (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations