Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSQRTE (vector, 2S)

Test 1: uops

Code:

  ursqrte v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000
1004303310011100010003769410001000100011000

Test 2: Latency 1->2

Code:

  ursqrte v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300379694101002001000620010004110000100
1020530066101071011000610010018300379694101002001000420010006110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100
1020430033101011011000010010000300379850101182001003220010004110000100
1020430033101011011000010010000300379694101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000703796941002020100042010006111000010
100243003310021211000002010000703796941002020100002010000111000010
100243003310021211000002010000703796941002020100002010000111000010
100243003310021211000002010000703796941002020100002010000111000010
100243003310021211000002010000703796941002020100002010000111000010
100243003310021211000002010000703796941002020100002010000111000010
100243003310021211000002010000703798501003820100262010000111000010
100243003310021211000002010000703796941002020100002010000111000010
15545440741461636139048195533809060703796941002020100002010000111000010
100243003310021211000002010000703796941002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  ursqrte v0.2s, v8.2s
  ursqrte v1.2s, v8.2s
  ursqrte v2.2s, v8.2s
  ursqrte v3.2s, v8.2s
  ursqrte v4.2s, v8.2s
  ursqrte v5.2s, v8.2s
  ursqrte v6.2s, v8.2s
  ursqrte v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020480049801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100
8020480035801011018000010080001300320005801012008000820080008180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024800428002321800022080004703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000673201008004620800402080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010
80024800358002121800002080000703200008002020800002080000118000010