Icestorm: URSQRTE (vector, 4S) measurements

Code:

  ursqrte v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000
1004	4033	1001	1	1000	1000	50608	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  ursqrte v0.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10006	200	10006	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10032	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509608	10100	200	10004	200	10004	1	10000	100
10204	40033	10101	101	10000	0	100	10000	300	509771	10117	200	10029	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10502	43780	10421	281	10004	136	237	10017	70	509608	10020	20	10004	20	0	10000	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	0	10029	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	67	509771	10037	20	10033	24666	16299	5832	11555	7366	5606	13208
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10028	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10
10024	40033	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	0	10004	11	0	10000	10

Test 3: throughput

Count: 8

Code:

  ursqrte v0.4s, v8.4s
  ursqrte v1.4s, v8.4s
  ursqrte v2.4s, v8.4s
  ursqrte v3.4s, v8.4s
  ursqrte v4.4s, v8.4s
  ursqrte v5.4s, v8.4s
  ursqrte v6.4s, v8.4s
  ursqrte v7.4s, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80205	160070	80110	101	80009	0	100	80022	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80205	160070	80110	101	80009	0	100	80022	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100
80205	160070	80110	101	80009	0	100	80022	300	1999769	80100	200	80004	200	80032	1	80000	100
80204	160035	80101	101	80000	0	100	80000	300	1999769	80100	200	80004	200	80004	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80004	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80037	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999932	80042	20	0	80032	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80004	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10
80024	160035	80021	21	80000	0	20	80000	0	70	0	1999769	80020	20	0	80000	20	80000	11	80000	10

URSQRTE (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations