Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSRA (vector, 16B)

Test 1: uops

Code:

  ursra v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  ursra v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020088110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100062020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000069076924710051200100472020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010

Test 3: Latency 1->2

Code:

  ursra v0.16b, v0.16b, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020088111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10025300661002721100062010031707689051002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ursra v0.16b, v8.16b, #3
  movi v1.16b, 0
  ursra v1.16b, v8.16b, #3
  movi v2.16b, 0
  ursra v2.16b, v8.16b, #3
  movi v3.16b, 0
  ursra v3.16b, v8.16b, #3
  movi v4.16b, 0
  ursra v4.16b, v8.16b, #3
  movi v5.16b, 0
  ursra v5.16b, v8.16b, #3
  movi v6.16b, 0
  ursra v6.16b, v8.16b, #3
  movi v7.16b, 0
  ursra v7.16b, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044046680109101800081008001230032005280112200800122001600241160000100
1602044010880110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244374880019118000810800123032005280022208001220160000116000010
1600244130480011118000010800003032000080010208000020160000116000010
1600244039780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244042180011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  ursra v0.16b, v16.16b, #3
  ursra v1.16b, v16.16b, #3
  ursra v2.16b, v16.16b, #3
  ursra v3.16b, v16.16b, #3
  ursra v4.16b, v16.16b, #3
  ursra v5.16b, v16.16b, #3
  ursra v6.16b, v16.16b, #3
  ursra v7.16b, v16.16b, #3
  ursra v8.16b, v16.16b, #3
  ursra v9.16b, v16.16b, #3
  ursra v10.16b, v16.16b, #3
  ursra v11.16b, v16.16b, #3
  ursra v12.16b, v16.16b, #3
  ursra v13.16b, v16.16b, #3
  ursra v14.16b, v16.16b, #3
  ursra v15.16b, v16.16b, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801341601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006402081601542001600642003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480141160017111600061016001003006400361600182001600122003200001016000010
16002480037160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010