Icestorm: URSRA (vector, 4H) measurements

Code:

  ursra v0.4h, v1.4h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0

Test 2: Latency 1->1

Code:

  ursra v0.4h, v1.4h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10107	101	10006	100	10031	300	768905	10100	200	10004	200	20088	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	67	0	769247	10051	20	0	10046	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  ursra v0.4h, v0.4h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10107	101	10006	100	10031	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	68	769247	10051	20	10048	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20096	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ursra v0.4h, v8.4h, #3
  movi v1.16b, 0
  ursra v1.4h, v8.4h, #3
  movi v2.16b, 0
  ursra v2.4h, v8.4h, #3
  movi v3.16b, 0
  ursra v3.4h, v8.4h, #3
  movi v4.16b, 0
  ursra v4.4h, v8.4h, #3
  movi v5.16b, 0
  ursra v5.4h, v8.4h, #3
  movi v6.16b, 0
  ursra v6.4h, v8.4h, #3
  movi v7.16b, 0
  ursra v7.4h, v8.4h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40546	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40119	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40101	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320200	80149	200	80049	200	160026	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43808	80020	11	80009	10	80013	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	41251	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40434	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40430	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40399	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40444	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40414	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	41689	80011	11	80000	10	80000	1559	96284	19760	242382	63067	3136	1902	59188	20	160000	1	160000	10
160024	40521	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40442	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  ursra v0.4h, v16.4h, #3
  ursra v1.4h, v16.4h, #3
  ursra v2.4h, v16.4h, #3
  ursra v3.4h, v16.4h, #3
  ursra v4.4h, v16.4h, #3
  ursra v5.4h, v16.4h, #3
  ursra v6.4h, v16.4h, #3
  ursra v7.4h, v16.4h, #3
  ursra v8.4h, v16.4h, #3
  ursra v9.4h, v16.4h, #3
  ursra v10.4h, v16.4h, #3
  ursra v11.4h, v16.4h, #3
  ursra v12.4h, v16.4h, #3
  ursra v13.4h, v16.4h, #3
  ursra v14.4h, v16.4h, #3
  ursra v15.4h, v16.4h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80076	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80151	160017	11	160006	0	10	160010	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640036	160018	20	160012	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80053	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640208	160064	20	160064	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

URSRA (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations