Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ursra v0.8h, v1.8h, #3
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 3033 | 1001 | 1 | 1000 | 1000 | 75905 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
ursra v0.8h, v1.8h, #3
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10205 | 30066 | 10107 | 101 | 10006 | 100 | 10031 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20012 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20096 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10025 | 30066 | 10027 | 21 | 10006 | 20 | 10031 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
Code:
ursra v0.8h, v0.8h, #3
movi v0.16b, 1
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 30033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 768905 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10004 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 30033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 768905 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
Count: 8
Code:
movi v0.16b, 0 ursra v0.8h, v8.8h, #3 movi v1.16b, 0 ursra v1.8h, v8.8h, #3 movi v2.16b, 0 ursra v2.8h, v8.8h, #3 movi v3.16b, 0 ursra v3.8h, v8.8h, #3 movi v4.16b, 0 ursra v4.8h, v8.8h, #3 movi v5.16b, 0 ursra v5.8h, v8.8h, #3 movi v6.16b, 0 ursra v6.8h, v8.8h, #3 movi v7.16b, 0 ursra v7.8h, v8.8h, #3
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5011
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
160204 | 40538 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160026 | 1 | 160000 | 100 |
160204 | 40108 | 80110 | 101 | 80009 | 100 | 80013 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
160204 | 40086 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 80012 | 200 | 160024 | 1 | 160000 | 100 |
Result (median cycles for code divided by count): 0.5052
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
160024 | 43798 | 80020 | 11 | 80009 | 10 | 80013 | 30 | 320052 | 80022 | 20 | 80012 | 20 | 160024 | 1 | 160000 | 10 |
160024 | 41231 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40378 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40416 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40422 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40405 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40420 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40406 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40418 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
160024 | 40416 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 80000 | 20 | 160000 | 1 | 160000 | 10 |
Count: 16
Code:
ursra v0.8h, v16.8h, #3 ursra v1.8h, v16.8h, #3 ursra v2.8h, v16.8h, #3 ursra v3.8h, v16.8h, #3 ursra v4.8h, v16.8h, #3 ursra v5.8h, v16.8h, #3 ursra v6.8h, v16.8h, #3 ursra v7.8h, v16.8h, #3 ursra v8.8h, v16.8h, #3 ursra v9.8h, v16.8h, #3 ursra v10.8h, v16.8h, #3 ursra v11.8h, v16.8h, #3 ursra v12.8h, v16.8h, #3 ursra v13.8h, v16.8h, #3 ursra v14.8h, v16.8h, #3 ursra v15.8h, v16.8h, #3
movi v16.16b, 17
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5002
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
160204 | 80094 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160107 | 101 | 160006 | 100 | 160010 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80084 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320124 | 1 | 160000 | 100 |
160204 | 80045 | 160105 | 101 | 160004 | 100 | 160008 | 1805 | 51371 | 20763 | 482644 | 125606 | 4327 | 2082 | 120673 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80035 | 160105 | 101 | 160004 | 100 | 160008 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320024 | 1 | 160000 | 100 |
160204 | 80109 | 160155 | 101 | 160054 | 100 | 160058 | 0 | 300 | 0 | 640036 | 160108 | 200 | 0 | 160012 | 200 | 320426 | 1 | 160000 | 100 |
Result (median cycles for code divided by count): 0.5002
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
160024 | 80342 | 160015 | 11 | 160004 | 10 | 160008 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80054 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640200 | 160062 | 20 | 0 | 160062 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160025 | 80071 | 160055 | 11 | 160044 | 10 | 160056 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 80035 | 160011 | 11 | 160000 | 10 | 160000 | 0 | 30 | 0 | 640000 | 160010 | 20 | 0 | 160000 | 20 | 320000 | 1 | 160000 | 10 |