Icestorm: USHLL (4S) measurements

Code:

  ushll v0.4s, v0.4h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  ushll v0.4s, v0.4h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	10006	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	202	10050	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	65	509580	10054	20	10041	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  ushll v0.4s, v8.4h, #3
  ushll v1.4s, v8.4h, #3
  ushll v2.4s, v8.4h, #3
  ushll v3.4s, v8.4h, #3
  ushll v4.4s, v8.4h, #3
  ushll v5.4s, v8.4h, #3
  ushll v6.4s, v8.4h, #3
  ushll v7.4s, v8.4h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40082	80105	101	80004	100	80008	34222	1287969	526621	318908	168192	80518	40268	74339	200	80012	1	80000	100
80204	40044	80105	101	80004	100	80008	0	300	0	320044	80110	200	0	80014	200	80014	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	40093	80029	21	80008	20	80012	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	80000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320200	80072	20	80062	20	0	80000	11	0	80000	10
80025	40069	80063	21	80042	20	80054	70	320000	80020	20	80000	20	0	80000	11	0	80000	10

USHLL (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations