Icestorm: USHR (vector, 16B) measurements

Code:

  ushr v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0
1004	2033	1001	1	1000	1000	50248	1000	1000	0	0	1000	1	0	1000	0

Test 2: Latency 1->2

Code:

  ushr v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	10006	1	10000	100
10205	20066	10109	101	10008	100	10034	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	0	10000	11	0	10000	10

Test 3: throughput

Count: 8

Code:

  ushr v0.16b, v8.16b, #3
  ushr v1.16b, v8.16b, #3
  ushr v2.16b, v8.16b, #3
  ushr v3.16b, v8.16b, #3
  ushr v4.16b, v8.16b, #3
  ushr v5.16b, v8.16b, #3
  ushr v6.16b, v8.16b, #3
  ushr v7.16b, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40097	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80107	101	80006	100	80010	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320220	80154	200	80058	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320044	80110	200	80014	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	0	80012	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40139	80027	21	80006	20	80010	70	320044	80030	20	80016	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320052	80032	20	80018	20	80048	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80049	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320184	80066	20	80046	20	80000	11	80000	10
80024	40108	80070	21	80049	20	80049	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320196	80069	20	80049	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320192	80068	20	80048	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80048	11	80000	10
80024	40259	80116	21	80095	20	80095	70	320368	80112	20	80092	20	80143	11	80000	10

USHR (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations