Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USQADD (scalar, H)

Test 1: uops

Code:

  usqadd h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  usqadd h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  usqadd h0, h0
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020088110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020008111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd h0, h8
  movi v1.16b, 0
  usqadd h1, h8
  movi v2.16b, 0
  usqadd h2, h8
  movi v3.16b, 0
  usqadd h3, h8
  movi v4.16b, 0
  usqadd h4, h8
  movi v5.16b, 0
  usqadd h5, h8
  movi v6.16b, 0
  usqadd h6, h8
  movi v7.16b, 0
  usqadd h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044046280110101800091008001330032005280112200800122001600261160000100
1602044010880110101800091008001330032005280112200800122001600241160000100
1602044010880110101800091008001330032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600941160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244417980019118000810800123032004880022208001220160216116000010
1600244139680085118007410800743032041680114208010420160000116000010
1600244040680011118000010800003032013680044208003420160000116000010
1600244052180048118003710800373032000080010208000020160146116000010
1600244042280011118000010800003032028880082208007220160000116000010
1600244041480011118000010800003032000080010208000020160000116000010
1600244055580046118003510800353032000080010208000020160000116000010
1600244080980155118014410801443032000080010208000020160000116000010
1600244042580011118000010800003032000080010208000020160000116000010
1600244042980011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  usqadd h0, h16
  usqadd h1, h16
  usqadd h2, h16
  usqadd h3, h16
  usqadd h4, h16
  usqadd h5, h16
  usqadd h6, h16
  usqadd h7, h16
  usqadd h8, h16
  usqadd h9, h16
  usqadd h10, h16
  usqadd h11, h16
  usqadd h12, h16
  usqadd h13, h16
  usqadd h14, h16
  usqadd h15, h16
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020480115160105101160004100160008300640044160110200160014200032002810160000100
16020480054160105101160004100160008300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032012410160000100
16020480035160107101160006100160010300640044160110200160014200032002410160000100
16020480036160107101160006100160010300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032002410160000100
16020480035160105101160004100160008300640036160108200160012200032002410160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480132160017111600061016001030640000160010201600002003200001016000010
16002480039160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003201201016000010
16002480035160011111600001016000030640000160010201600002003200001016000010