Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USQADD (vector, 16B)

Test 1: uops

Code:

  usqadd v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  usqadd v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020010110000100
1020430033101011011000010010000300768905101002001000620220092210000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  usqadd v0.16b, v0.16b
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010004200200081101000010
10024300331002121100000201000070768905100202010000200200001101000010
10024300331002121100000201000070768905100202010000200200001101000010
10024300331002121100000201000070768905100202010000200200001101000010
10025300661002721100060201003170768905100202010000200200001101000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd v0.16b, v8.16b
  movi v1.16b, 0
  usqadd v1.16b, v8.16b
  movi v2.16b, 0
  usqadd v2.16b, v8.16b
  movi v3.16b, 0
  usqadd v3.16b, v8.16b
  movi v4.16b, 0
  usqadd v4.16b, v8.16b
  movi v5.16b, 0
  usqadd v5.16b, v8.16b
  movi v6.16b, 0
  usqadd v6.16b, v8.16b
  movi v7.16b, 0
  usqadd v7.16b, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044050680109101800081008001230032005280112200800122001600241160000100
1602044011580110101800091008001330032005280112200800122001600261160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5057

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244381780020118000910800130300320000800102008000020160000116000010
1600244114480011118000010800000300320000800102008000020160288116000010
1600244043980011118000010800000300320000800102008000020160000116000010
1600244042480011118000010800000300320000800102008000020160000116000010
1600244045180011118000010800000300320000800102008000020160000116000010
1600244044180011118000010800000300320000800102008000020160000116000010
1600244046280011118000010800000300320000800102008000020160000116000010
1600244043180011118000010800000300320000800102008000020160000116000010
1600254378180056118004510800490300320056800232008001320160000116000010
1600244043380011118000010800001807584334219823012062387417420945752920160098116000010

Test 5: throughput

Count: 16

Code:

  usqadd v0.16b, v16.16b
  usqadd v1.16b, v16.16b
  usqadd v2.16b, v16.16b
  usqadd v3.16b, v16.16b
  usqadd v4.16b, v16.16b
  usqadd v5.16b, v16.16b
  usqadd v6.16b, v16.16b
  usqadd v7.16b, v16.16b
  usqadd v8.16b, v16.16b
  usqadd v9.16b, v16.16b
  usqadd v10.16b, v16.16b
  usqadd v11.16b, v16.16b
  usqadd v12.16b, v16.16b
  usqadd v13.16b, v16.16b
  usqadd v14.16b, v16.16b
  usqadd v15.16b, v16.16b
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801871601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248012616001511160004010160008306400361600182016001220320000116000010
1600248005116001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248004216001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320120116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010
1600248003516001111160000010160000306402081600642016006220320000116000010
1600248016316001711160006010160010306400001600102016000020320000116000010
1600248003516001111160000010160000306400001600102016000020320000116000010