Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USQADD (vector, 2S)

Test 1: uops

Code:

  usqadd v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  usqadd v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000707689051002020100062020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000687710891015220101622020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  usqadd v0.2s, v0.2s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000307769247101332021004520020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020008111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd v0.2s, v8.2s
  movi v1.16b, 0
  usqadd v1.2s, v8.2s
  movi v2.16b, 0
  usqadd v2.2s, v8.2s
  movi v3.16b, 0
  usqadd v3.2s, v8.2s
  movi v4.16b, 0
  usqadd v4.2s, v8.2s
  movi v5.16b, 0
  usqadd v5.2s, v8.2s
  movi v6.16b, 0
  usqadd v6.2s, v8.2s
  movi v7.16b, 0
  usqadd v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048980109101800081008001230032005680113200800132001600241160000100
1602044011080110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602054013180147101800461008005030032005280112200800122001600241160000100
1602044008680109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244375880020118000910800133032019280057208004720160024116000010
1600244135180054118004310800473032057680154208014420160000116000010
1600244048680048118003710800373032034080094208008420160000116000010
1600244048980011118000010800003032000080010208000020160000116000010
1600244037580011118000010800003032000080010208000020160000116000010
1600254133080124118011310801173032014880047208003720160000116000010
1600244064480081118007010800703032014480046208003620160070116000010
1600244041780011118000010800003032014080045208003520160146116000010
1600244340780225118021410802143032014080045208003520160078116000010
1600244177980083118007210800723032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  usqadd v0.2s, v16.2s
  usqadd v1.2s, v16.2s
  usqadd v2.2s, v16.2s
  usqadd v3.2s, v16.2s
  usqadd v4.2s, v16.2s
  usqadd v5.2s, v16.2s
  usqadd v6.2s, v16.2s
  usqadd v7.2s, v16.2s
  usqadd v8.2s, v16.2s
  usqadd v9.2s, v16.2s
  usqadd v10.2s, v16.2s
  usqadd v11.2s, v16.2s
  usqadd v12.2s, v16.2s
  usqadd v13.2s, v16.2s
  usqadd v14.2s, v16.2s
  usqadd v15.2s, v16.2s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160204800691601051011600040100160008300640036160108200160012200032002810160000100
160205800701601431011600420100160054300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002810160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100
160204800351601051011600040100160008300640036160108200160012200032002410160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480145160017111600061016001003006400361600182001600122003200001016000010
16002480054160011111600001016000003006402081600642001600632003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002580070160053111600421016005403006400001600102001600002003200001016000010
160024800351600111116000010160000428789629896402411611749224901600672003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010
16002480035160011111600001016000003006400001600102001600002003200001016000010