Icestorm: USQADD (vector, 2S) measurements

Code:

  usqadd v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  usqadd v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	68	771089	10152	20	10162	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  usqadd v0.2s, v0.2s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10045	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd v0.2s, v8.2s
  movi v1.16b, 0
  usqadd v1.2s, v8.2s
  movi v2.16b, 0
  usqadd v2.2s, v8.2s
  movi v3.16b, 0
  usqadd v3.2s, v8.2s
  movi v4.16b, 0
  usqadd v4.2s, v8.2s
  movi v5.16b, 0
  usqadd v5.2s, v8.2s
  movi v6.16b, 0
  usqadd v6.2s, v8.2s
  movi v7.16b, 0
  usqadd v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40489	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160024	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160205	40131	80147	101	80046	100	80050	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43758	80020	11	80009	10	80013	30	320192	80057	20	80047	20	160024	1	160000	10
160024	41351	80054	11	80043	10	80047	30	320576	80154	20	80144	20	160000	1	160000	10
160024	40486	80048	11	80037	10	80037	30	320340	80094	20	80084	20	160000	1	160000	10
160024	40489	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40375	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	41330	80124	11	80113	10	80117	30	320148	80047	20	80037	20	160000	1	160000	10
160024	40644	80081	11	80070	10	80070	30	320144	80046	20	80036	20	160070	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320140	80045	20	80035	20	160146	1	160000	10
160024	43407	80225	11	80214	10	80214	30	320140	80045	20	80035	20	160078	1	160000	10
160024	41779	80083	11	80072	10	80072	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  usqadd v0.2s, v16.2s
  usqadd v1.2s, v16.2s
  usqadd v2.2s, v16.2s
  usqadd v3.2s, v16.2s
  usqadd v4.2s, v16.2s
  usqadd v5.2s, v16.2s
  usqadd v6.2s, v16.2s
  usqadd v7.2s, v16.2s
  usqadd v8.2s, v16.2s
  usqadd v9.2s, v16.2s
  usqadd v10.2s, v16.2s
  usqadd v11.2s, v16.2s
  usqadd v12.2s, v16.2s
  usqadd v13.2s, v16.2s
  usqadd v14.2s, v16.2s
  usqadd v15.2s, v16.2s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80069	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320028	1	0	160000	100
160205	80070	160143	101	160042	0	100	160054	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320028	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80145	160017	11	160006	10	160010	0	30	0	640036	160018	20	0	160012	20	0	320000	1	0	160000	10
160024	80054	160011	11	160000	10	160000	0	30	0	640208	160064	20	0	160063	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160025	80070	160053	11	160042	10	160054	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	428	7896	2989	640241	161174	922	490	160067	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10

USQADD (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations