Icestorm: USQADD (vector, 8H) measurements

Code:

  usqadd v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	31265	21295	2424	14525	9893	1151	17365
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0
1004	3033	1001	1	1000	1000	75905	1000	1000	0	0	2000	1	0	1000	0

Test 2: Latency 1->1

Code:

  usqadd v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	769247	10051	20	0	10044	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  usqadd v0.8h, v0.8h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20160	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd v0.8h, v8.8h
  movi v1.16b, 0
  usqadd v1.8h, v8.8h
  movi v2.16b, 0
  usqadd v2.8h, v8.8h
  movi v3.16b, 0
  usqadd v3.8h, v8.8h
  movi v4.16b, 0
  usqadd v4.8h, v8.8h
  movi v5.16b, 0
  usqadd v5.8h, v8.8h
  movi v6.16b, 0
  usqadd v6.8h, v8.8h
  movi v7.16b, 0
  usqadd v7.8h, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40522	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320196	80148	200	80048	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160092	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40623	80217	101	80116	100	80120	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43797	80020	11	80009	10	80013	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	41240	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40424	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40401	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160100	1	160000	10
160024	40475	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40410	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40412	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40412	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10
160024	40408	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  usqadd v0.8h, v16.8h
  usqadd v1.8h, v16.8h
  usqadd v2.8h, v16.8h
  usqadd v3.8h, v16.8h
  usqadd v4.8h, v16.8h
  usqadd v5.8h, v16.8h
  usqadd v6.8h, v16.8h
  usqadd v7.8h, v16.8h
  usqadd v8.8h, v16.8h
  usqadd v9.8h, v16.8h
  usqadd v10.8h, v16.8h
  usqadd v11.8h, v16.8h
  usqadd v12.8h, v16.8h
  usqadd v13.8h, v16.8h
  usqadd v14.8h, v16.8h
  usqadd v15.8h, v16.8h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80077	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320028	1	0	160000	100
160204	80045	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160205	80071	160143	101	160042	100	160054	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80212	160017	11	160006	10	160010	0	30	0	640036	160018	20	0	160012	20	320000	1	160000	10
160024	80057	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80045	160011	11	160000	10	160000	0	30	0	640200	160062	20	0	160062	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640204	160063	20	0	160061	20	320000	1	160000	10
160024	80037	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10

USQADD (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations