Icestorm: USRA (vector, 8B) measurements

Code:

  usra v0.8b, v1.8b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  usra v0.8b, v1.8b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20088	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10006	20	20012	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20080	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	4674	229775	85381	437594	18530	11084	5232	5800	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  usra v0.8b, v0.8b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usra v0.8b, v8.8b, #3
  movi v1.16b, 0
  usra v1.8b, v8.8b, #3
  movi v2.16b, 0
  usra v2.8b, v8.8b, #3
  movi v3.16b, 0
  usra v3.8b, v8.8b, #3
  movi v4.16b, 0
  usra v4.8b, v8.8b, #3
  movi v5.16b, 0
  usra v5.8b, v8.8b, #3
  movi v6.16b, 0
  usra v6.8b, v8.8b, #3
  movi v7.16b, 0
  usra v7.8b, v8.8b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40476	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160100	1	160000	100
160204	40096	80110	101	80009	100	80013	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160106	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	43842	80020	11	80009	10	80013	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	41326	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160025	40503	80055	11	80044	10	80048	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40406	80011	11	80000	10	80000	30	320056	80023	20	80013	20	0	160000	1	0	160000	10
160024	40430	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40402	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40432	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40399	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10

Test 5: throughput

Count: 16

Code:

  usra v0.8b, v16.8b, #3
  usra v1.8b, v16.8b, #3
  usra v2.8b, v16.8b, #3
  usra v3.8b, v16.8b, #3
  usra v4.8b, v16.8b, #3
  usra v5.8b, v16.8b, #3
  usra v6.8b, v16.8b, #3
  usra v7.8b, v16.8b, #3
  usra v8.8b, v16.8b, #3
  usra v9.8b, v16.8b, #3
  usra v10.8b, v16.8b, #3
  usra v11.8b, v16.8b, #3
  usra v12.8b, v16.8b, #3
  usra v13.8b, v16.8b, #3
  usra v14.8b, v16.8b, #3
  usra v15.8b, v16.8b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80045	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160107	101	160006	100	160010	2224	52057	24446	634472	164658	5480	2573	158635	200	320028	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320028	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80146	160017	11	160006	10	160010	30	640036	160018	20	160012	20	320000	1	160000	10
160024	80050	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320124	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160025	80070	160051	11	160040	10	160052	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

USRA (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations