Icestorm: USUBL2 (vector, 8H) measurements

Code:

  usubl2 v0.8h, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.012

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2135	1025	1	1024	1072	50780	1036	1042	2000	1	1000
1004	2136	1025	1	1024	1072	50780	1036	1041	2000	1	1000
1004	2135	1025	1	1024	1072	51300	1070	1075	2246	1	1000
1004	2084	1013	1	1012	1036	51312	1072	1081	2246	1	1000
1004	2085	1013	1	1012	1036	50248	1000	1000	2166	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2084	1013	1	1012	1036	50248	1000	1000	2000	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1040	2086	1	1000
1004	2136	1025	1	1024	1072	50780	1036	1041	2242	1	1000
1004	2239	1049	1	1048	1144	51844	1108	1123	2000	1	1000

Test 2: Latency 1->2

Code:

  usubl2 v0.8h, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0447

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	306	511908	10282	202	10214	204	20264	3	10000	100
10204	20446	10205	109	10096	108	10288	327	514020	10432	208	10390	208	20672	5	10000	100
10204	20448	10203	107	10096	106	10288	320	513488	10394	206	10336	208	20750	5	10000	100
10204	20495	10215	107	10108	106	10324	326	513488	10396	208	10340	206	20760	4	10000	100
10204	20601	10242	110	10132	109	10396	335	514568	10470	210	10418	206	20758	4	10000	100
10204	20498	10215	107	10108	106	10324	321	514020	10430	206	10375	208	20924	5	10000	100
10204	20497	10213	105	10108	104	10324	331	514036	10433	210	10379	210	20754	5	10000	100
10204	20653	10257	113	10144	112	10432	313	513488	10392	204	10338	202	20422	2	10000	100
10204	20342	10181	109	10072	108	10216	334	514568	10470	212	10420	206	21006	3	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  usubl2 v0.8h, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	169	14625	7760	509580	10560	581	200	10048	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10004	20	20008	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20012	11	10000	10
10024	20033	10021	21	10000	0	20	10000	67	509780	10056	20	10040	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509780	10056	20	10042	22	20168	12	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	22	20086	12	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20084	11	10000	10
10024	20033	10021	21	10000	0	20	10000	70	509248	10020	20	10000	20	20086	11	10000	10

Test 4: throughput

Count: 8

Code:

  usubl2 v0.8h, v8.16b, v9.16b
  usubl2 v1.8h, v8.16b, v9.16b
  usubl2 v2.8h, v8.16b, v9.16b
  usubl2 v3.8h, v8.16b, v9.16b
  usubl2 v4.8h, v8.16b, v9.16b
  usubl2 v5.8h, v8.16b, v9.16b
  usubl2 v6.8h, v8.16b, v9.16b
  usubl2 v7.8h, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40057	80105	101	80004	100	80008	300	320208	80154	200	80064	200	160026	1	80000	100
80204	40044	80107	101	80006	100	80010	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320044	80110	200	80013	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40129	80029	21	80008	20	80012	68	320052	80032	20	80018	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40397	80253	21	80232	20	80232	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40048	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160094	11	80000	10
80024	40034	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160186	11	80000	10
80024	40034	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40179	80116	21	80095	20	80095	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40107	80069	21	80048	20	80048	65	320000	80020	20	80000	20	160000	11	80000	10

USUBL2 (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations