Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

XTN2 (4S)

Test 1: uops

Code:

  xtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000

Test 2: Latency 1->1

Code:

  xtn2 v0.8h, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020012110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000307509580101362021004820020012110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420187101371011003610010108300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->2

Code:

  xtn2 v0.8h, v0.4s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020520066101091011000810010034300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  xtn2 v0.8h, v8.4s
  movi v1.16b, 0
  xtn2 v1.8h, v8.4s
  movi v2.16b, 0
  xtn2 v2.8h, v8.4s
  movi v3.16b, 0
  xtn2 v3.8h, v8.4s
  movi v4.16b, 0
  xtn2 v4.8h, v8.4s
  movi v5.16b, 0
  xtn2 v5.8h, v8.4s
  movi v6.16b, 0
  xtn2 v6.8h, v8.4s
  movi v7.16b, 0
  xtn2 v7.8h, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044047880109101800081008001230032005280112200800122001600241160000100
1602054015380144101800431008004730032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122021600922160000100
1602044008680109101800081008001230032005280112200800122001600961160000100
1602044014680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602054012080143101800421008004630032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244390880019118000810800123032019680058208004820160026116000010
1600244121380011118000010800003032000080010208000020160000116000010
1600244042980011118000010800003032000080010208000020160000116000010
1600244092180011118000010800003032000080010208000020160000116000010
1600244043480011118000010800003032000080010208000020160000116000010
1600244042380011118000010800003032000080010208000020160282116000010
1600244041580011118000010800003032000080010208000020160072116000010
1600244042080011118000010800003032000080010208000020160000116000010
1600244038680011118000010800003032000080010208000020160050116000010
1600244041880011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  xtn2 v0.8h, v16.4s
  xtn2 v1.8h, v16.4s
  xtn2 v2.8h, v16.4s
  xtn2 v3.8h, v16.4s
  xtn2 v4.8h, v16.4s
  xtn2 v5.8h, v16.4s
  xtn2 v6.8h, v16.4s
  xtn2 v7.8h, v16.4s
  xtn2 v8.8h, v16.4s
  xtn2 v9.8h, v16.4s
  xtn2 v10.8h, v16.4s
  xtn2 v11.8h, v16.4s
  xtn2 v12.8h, v16.4s
  xtn2 v13.8h, v16.4s
  xtn2 v14.8h, v16.4s
  xtn2 v15.8h, v16.4s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800761601051011600041001600083006400361601082001600122003200281160000100
160204800341601071011600061001600103006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160205800681601391011600381001600503006400441601102001600142003200281160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802021600171116000610160010306400361600182016001220320024116000010
160024800451600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320024116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010